1. Field of the Invention
The present invention relates to a pseudo differential output buffer, a memory chip and a memory system, and more particularly to an output buffer of a memory chip to drive a data transmission line between a memory module and a memory controller. This application claims priority under 35 USC § 119 to Korean Patent Application No. 2004-83040, filed on Oct. 18, 2004, the contents of which are herein incorporated by reference in their entirety for all purposes.
2. Description of the Related Art
As computers and networks have increased operating speeds, it is desirable that a memory such as a dynamic random access memory (DRAM) operates at high speed and has a large capacity. In a computer system, a central processing unit (CPU) and a memory are electrically connected to each other via a memory controller. The memory may include a memory module mounted on a motherboard. In that case, the memory controller and the memory module are electrically connected via a transmission line formed in a printed circuit board (PCB). Therefore, the signal attenuation of the transmission line may be increased with an increase of a distance between the memory controller and the memory module.
Methods of driving an output buffer include a push-pull driver method, an open drain driver method, and a differential amplifying driver method. In a DDR type memory module, 64 data lines may be used. Accordingly, a push-pull type output buffer or an open drain type output buffer may be used to account for a number of the data lines. In a Rambus DRAM memory module or a fully buffered dual in-line memory module (FB-DIMM), a differential amplifying method may be used to allow for high-speed operation. The Rambus DRAM DIMM may have 32 data lines for 16 differential pairs of packets. The FB-DIMM memory module may have 14 differential pairs for northbound packets and 10 differential pairs for southbound packets so that the FB-DIMM memory module may include a total of 48 lines.
FIG. 1 is a circuit diagram illustrating a conventional differential driving method of a data bus.
Referring to FIG. 1, a driver 10 and a receiver 20 are coupled via transmission lines 30, a pair of which are allotted to each bit of data. For example, 16 pairs of transmission lines, (32 transmission lines) are needed for 16-bit data. 32 input and output terminals DQ are also needed.
The driver 10 includes input transistors MN1 and MN2 that receive a differential input pair DOUT and DOUTB, respectively, and transistors MP1 and MP2 that are controlled by an output enable signal OEN. The driver 10 further includes output loads Z01 and Z02 that are equal to each other.
The receiver 20 includes termination pull up resistors Z03 and Z04, which are equal to each other and act as termination loads of the transmission line 30, transistors MP3 and MP4 that are controlled by an input enable signal IEN and a data input circuit 22.
FIG. 2 is a waveform diagram illustrating a signal in the data bus in FIG. 1 and FIG. 3 is a circuit diagram illustrating a connection structure of power supply lines of a plurality of data output buffers.
Referring to FIG. 2 in the differential driving method, 16 output buffers may simultaneously operate to drive 16 -bit data to allow substantially identical driving currents to continuously flow therethrough. For example, as shown in FIG. 3, each output buffer may consume a driving current Id of about 10 mA, and when a power supply voltage line VDDQ has an impedance Rvddq of about 0.3Ω, a voltage drop ΔV may be generated by Id×16×Rvddq (i.e., 10 mA×16×0.3=48 mV). As a magnitude of the voltage drop ΔV remains constant regardless of an output pattern of the data, simultaneous switching output noise (SSO noise) may not be generated. Therefore, signal integrity may be improved.
However, as two data output terminals are required for one output buffer, the number of data output terminals required is twice the number of data bits. The increase in the number of data output terminals may result in an increase in the chip size and cause difficulty in the layout configuration of the input and output pads.
FIG. 4 is a circuit diagram illustrating a conventional open drain type driving method of a data bus.
Referring to FIG. 4, a driver 40 and a receiver 50 are coupled via a data transmission line 60, a respective one of which is allotted to each corresponding bit of data. For example, 16 transmission lines and 16 output terminals DQ are required for 16-bit data.
The driver 40 includes a transistor MN4 for receiving the input data DOUT and a bias transistor MN5 that are serially coupled between the output terminal DQ and a ground voltage.
The receiver 50 includes a termination pull up resistor Z05 that acts as a termination load of the transmission line 60, a transistor MP5 that operates based on the input enable signal IEN and a data input and output circuit 52.
FIG. 5 is a waveform diagram illustrating a signal in the data bus in FIG. 4.
As shown in FIG. 5, the magnitude of the voltage drop ΔV varies according to the number of output buffers that are turned on.
As the magnitude of the voltage drop ΔV is varied according to a variance in the output pattern of the data, the simultaneous switching output noise (SSO noise) may be generated. Therefore, the signal integrity may be degraded. However, because a respective one output terminal is allotted to each corresponding bit of data, a total number of data output terminals is decreased by one half compared with the differential output method.
Therefore, an output buffer that has an output terminal corresponding to each bit of output data while maintaining the signal integrity substantially equal to the signal integrity of the differential output buffer is needed.